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28:4 lvds receiver CS5825 block diagram general description century semiconductor inc. features usa: 1485 saratoga ave. #200 san jose, ca, 95129 tel: 408-973-8388 fax: 408-973-9388 sales@century-semi.com sales@century-semi.com.tw www.century-semi.com rev.0.0 may 2001 page 1 of 13 century semiconductor, inc. taiwan: no. 2, industry east rd. 3rd, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 CS5825 CS5825 receives four lvds data channels and one lvds clock channel. each data channel is deserialized into 7-bit parallel data bus for output. the clock channel is used for frame sync and fed into an internal pll that generates the 7x serial clock used in the deserializer. a digital phase alignment circuit can generate the sampling clock of the deserializer front-end. the frame sync clock aligned to the output 7-bit data is also output for timing reference. CS5825 supports open-safe design of lvds when the input is not connected to lvds drivers and the receiver outputs are forced low. putting CS5825 into inhibit mode by a shutdown control (shtdnn) signal can lower power consumption. ? four 7-bit serial data lvds channels and one clock lvds channel. ? compatible with ansi tia/eia-644 lvds stan- dard. ? wide serial clocking speed ranges from 31mhz to 68mhz. ? support open-safe lvds design. ? fully integrated on-chip pll and digital phase alignment provide accurate deserializer operation. ? support power-down mode. ? 5v/3.3v tolerant data input. ? single 3.3v supply operation. ? cmos low power consumption. ? functional compatible with ds90cf384 and sn75lvds86. ? available in 56-pin tssop package. parallel-in serial-out 7-bit shift register parallel-in serial-out 7-bit shift register parallel-in serial-out 7-bit shift register din clk phase lock loop 7xclk control logic d19,d20,d21,d22, d27,d5,d10,d11, shtdnn CS5825 din clk din clk parallel-in serial-out 7-bit shift register din clk d0,d1,d2,d3, d4,d6,d7 d8,d9,d12,d13, d14,d15,d18 d24,d25,d26 d16,d17,d23 bip bim cip cim dip dim ckip ckim aip aim and phase aligner clkout .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 2 of 13 pin connection diagram figure-1 56-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 d22 d23 d24 vss d25 d26 d27 lvds_vss aim aip bim bip lvds_vdd lvds_vss cim cip ckim ckip dim dip lvds_vss pll_vss pll_vdd pll_vss shtdnn clkout d0 vss CS5825 vdd d21 d20 d19 vss d18 d17 d16 vdd d15 d14 d13 vss d12 d11 d10 vdd d9 d8 d7 vss d6 d5 d4 d3 vdd d2 d1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 3 of 13 pin description name pin description aip, aim i lvds data channel a input. these are differential lvds inputs for a channel corresponds to d0, d1, d2, d3, d4, d6, d7. aip is the positive data input and aim is the negative input. bip, bim i lvds data channel b output. these are differential lvds inputs for b channel corresponds to d8, d9, d12, d13, d14, d15, d18. cip, cim i lvds data channel c output. these are differential lvds outputs for c channel corresponds to d19, d20, d21, d22, d24, d25, d26. dip, dim i lvds data channel c output. these are differential lvds outputs for d channel corresponds to d27, d5, d10, d11, d16, d17, d23. ckip, ckim i lvds clock channel input. these are differential lvds input for the frame sync clock. the clock is sent to an on-chip pll to generate 7x serial clock; an phase aligner is used to align the deserializer clock. d0,d1,d2,d3,d4, d6, d7 o parallel data output for lvds channel a. d[0] is lsb and d[7] is msb. msb is shifted in first. d8,d9,d12,d13, d14,d15,d18 o parallel data output for lvds channel b. d[8] is lsb and d[18] is msb. d19,d20,d21,d22 ,d24,d25,d26 o parallel data output for lvds channel c. d[19] is lsb and d[26] is msb. d27,d5,d10,d11, d16,d17,d23 o parallel data output for lvds channel c. d[19] is lsb and d[23] is msb. clkout o parallel data clock output. this clock signal recovered clock for data output reference. the falling edge should be used as the strobe for the next stage. shtdnn i shutdown control (low active). when shtdnn is low, the internal pll is put into inhibit mode and all data outputs are forced low. this also resets all internal registers. for normal operation, shtdnn should be set to high. vdd p positive power supply for ttl outputs. a 3.3v supply should be used. vss p negative power supply. connect to 0v. lvds_vdd p positive power supply for lvds inputs. lvds_vss p negative power supply for lvds inputs. pll_vdd p positive power supply for pll. pll_vss p negative power supply for pll. .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 4 of 13 functional description serial-in parallel-out 7-bit shift register it receives the serial data from the transmitter. it uses the 7xclk to strobe the serial data and sends 7-bit parallel data with input clock?s frequency. phase lock loop and phase aligner the pll generates the seven times input clock which is used for deserialized. the phase aligner is used for synchronous the input clock and output. control logic there are two modes in this circuit. one is normal mode, and another is power down mode. two modes are controlled by the control signal ?shtdnn?. if shtdnn is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. in the power down mode, every block is off to make sure the least power consumption. .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 5 of 13 recommended operating conditions timing requirements note: parameter t c is defined as the mean duration of a minimum of 32000 clock cycles. electrical characteristics over recommended operating conditions (unless otherwise noted) symbol parameter min typ max unit v cc supply voltage 33.33.6v v ih (shtdn ) high-level input voltage 2- - v v il (shtdn ) low-level input voltage --0.8v receiver input range 0-2.4v t a operating free-air temperature 0-70 c symbol parameter min typ max unit t c cycle time, input clock* 14.7 t c 32.4 ns t su1 setup time, input 600 - - ps t h1 hold time, input 600 - - ps symbol parameter condition min typ max unit v it+ differential input high threshold voltage - - 100 mv v it- differential input low threshold voltage -100 - - mv v oh high-level output voltage i oh = -4ma 2.4 - - v v ol low-level output voltage i ol = 4ma - - 0.4 v i cc quiescent current (average) disabled (power down mode), all inputs open -280- a enabled, anp = 1v, anm = 1.4v, t c = 15.38ns -5872ma enabled, c l = 8 pf, grayscale pattern, t c = 15.38ns -69-ma enabled, c l = 8 pf, grayscale pattern, t c = 15.38ns -94-ma i ih high-level input current (shtdn ) v ih = v cc --20 a i il low-level input current (shtdn ) v il = 0 - - 20 a i i input current (lvds input terminals a and clkin) 0 v 1 2.4v - - 10 a i oz high-impedance output current v o = 0 or v cc --10 a .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 6 of 13 switching characteristics over recommended operating conditions (unless otherwise noted) switching characteristics symbol parameter condition min typ max unit t su2 setup time, d0 - d20 valid to clkout c l = 8pf (figure-3) 5- -ns t h2 hold time, clkout to d0 - d20 valid 5- -ns t rskm receive input skew margin t c = 15.38 ns (0.2%), input clock jitter < 50 ps (figure-4) 490 - - ps t d delay time, clkin to clkout t c = 15.38 ns (0.2%), c l = 8 pf -3.7- ns ? t c(o) cycle time, change in output clock period# - 100 - ps t en enable time, shtdn to dn valid figure-6 - 1 - ms t dis disable time, shtdn to off state figure-7 - 400 - ns t t transition time, output (10% to 90% t r or t f ) cl = 8pf - 3 - ns t w pulse duration, output clock - - 0.43t c -ns symbol parameter min typ max unit lht low to high transition time -2.25ns hlt high to low transitions time -2.25ns pos0 input strobe position for bit 0 (f = 65mhz) 0.7 1.1 1.4 ns pos1 input strobe position for bit 1 (f = 65mhz) 2.9 3.3 3.6 ns pos2 input strobe position for bit 2 (f = 65mhz) 5.1 5.5 5.8 ns pos3 input strobe position for bit 3 (f = 65mhz) 7.3 7.7 8.0 ns pos4 input strobe position for bit 4 (f = 65mhz) 9.5 9.9 10.2 ns pos5 input strobe position for bit 5 (f = 65mhz) 11.7 12.1 12.4 ns pos6 input strobe position for bit 6 (f = 65mhz) 13.9 14.3 14.6 ns skm rxin skew margin (f = 65mhz) 400 - - ps cop rxclk out period 14.7 - 32.2 ns coh rxclk out high time (f = 65mhz) 7.5 - - ns col rxckk out low time (f = 65mhz) 3.5 - - ns src rxout setup to rxclkout (f = 65mhz) 2.5 - - ns hrc rxout hold to rxclkout (f = 65mhz) 2.5 - - ns ccd rxclk in to rxclk out delay 5-9ns plls phase lock loop set --10ms pdd power down delay --1 s .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 7 of 13 electrical characteristics symbol parameter condition min typ max unit irccg receiver supply current c l = 8pf, f = 65mhz (worst case pattern) ---ma irccw receiver supply current c l = 8pf,f = 65mhz (grayscale pattern) ---ma irccs receiver power down supply current power down = low - 200 300 a .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 8 of 13 timing diagrams figure-2 cmos/ttl output load figure-3 cmos/ttl output transition times figure-4 setup/hold and high/low times cs 8pf cmos/ttl output lht hlt 20% 80% 20% 80% cop src coh 2.0v setup hrc col 0.8v 2.0v 2.0v 2.0v hold clkout d[20:0] .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 9 of 13 test pattern figure-5 16-grayscale testing pattern waveforms figure-6 the worst-case testing pattern waveforms figure-7 setup and hold time waveforms clkin d0, 6, 12 d1, 7, 13 d2, 8, 14 d3, 9, 15 d18, 19, 20 d4, 5, 10, 11, 16, 17 clkin/clkout even dn odd dn t su2 t su2 70% v oh 30% v oh 70% v oh 30% v oh t h2 d0 - d20 clkout .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 10 of 13 parameter measurement information figure-8 receiver input skew margin, setup/hold time, and delay time definitions and an t d t c 4/7 t c t (rskm) (see note a) t su1 t h1 3/7 t c t (rskm) (see note a) an clkin 7 x clk clkout (internal) t w t w v oh 1.4v 300mv 20% v ol t d t r < 1ns 80% clkin or an 0v -300mv note a: clkin is advanced or delayed with respect to data until errors are observed at the receiver outputs. the advance or delay is then reduced until there are no data errors observed. the magnitude of the advance or delay is t (rskm) . clkout .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 11 of 13 figure-9 clock-in to clock-out delay figure-10 phase lock loop stable time figure-11 power down delay ccd vdiff=0v ckip/ckim clkout plls power down vcc ckip/ckim rxclk out 2v 3v 2v pdd low 1.5v power down (low active) rxclk in rxout .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 12 of 13 figure-12 strobe positions of lvds inputs figure-13 skew margin of lvds data inputs pos0 max. pos0 min. pos1 min pos1 max. pos2 min. pos2 max. pos3 min. pos3 max. pos4 min. pos4 max. pos5 min. pos5 max. pos6 min. pos6 max. ckip/ckim ai bi ci min. max. min. max. rskm min. max. c rskm rsposn *ip or *im *im or *ip ~1.4v ~1.0v ideal strobe position tpposn tpposn+1 .com .com .com .com .com 4 .com u datasheet
CS5825 century semiconductor inc. page 13 of 13 package outline (56-pin tssop) symbol dimensions in millimeters dimensions in inches min nom max min nom max a 1.05 - 1.20 0.041 - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 - 0.90 - - 0.035 - b 0.17 0.20 0.27 0.007 0.008 0.010 c 0.09 0.15 0.20 0.004 0.006 0.008 d 13.90 14.00 14.10 0.547 0.551 0.555 e 7.80 8.10 8.40 0.307 0.319 0.330 e1 6.00 6.10 6.20 0.236 0.240 0.244 e - 0.50 - - 0.0197 - l 0.50 - 0.75 0.020 - 0.030 0 - 7 0 - 7 e e1 e a1 a2 a d l c b .com .com .com .com 4 .com u datasheet

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